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HUF76419D3, HUF76419D3S
Data Sheet October 1999 File Number 4668.1
20A, 60V, 0.043 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging
JEDEC TO-251AA JEDEC TO-252AA
Features
* Ultra Low On-Resistance - rDS(ON) = 0.037, VGS = 10V - rDS(ON) = 0.043, VGS = 5V * Simulation Models - Temperature Compensated PSPICE(R) and SABER(c) Electrical Models - Spice and SABER(c) Thermal Impedance Models - www.semi.Intersil.com * Peak Current vs Pulse Width Curve * UIS Rating Curve
DRAIN (FLANGE)
SOURCE DRAIN GATE GATE SOURCE
DRAIN (FLANGE)
HUF76419D3
HUF76419D3S
Symbol
D
* Switching Time vs RGS Curves
Ordering Information
PART NUMBER PACKAGE TO-251AA TO-252AA BRAND 76419D 76419D HUF76419D3 HUF76419D3S
G
S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76419D3ST
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified HUF76419D3, HUF76419D3S UNITS V V V A A A A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTE:
60 60 16 20 20 20 19 Figure 4 Figures 6, 17, 18 75 0.5 -55 to 175 300 260
W W/oC
oC oC oC
1. TJ = 25oC to 150oC. CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
4-1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. UltraFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. SABER(c) is a Copyright of Analogy Inc. 1-888-INTERSIL or 407-727-9207 | Copyright (c) Intersil Corporation 1999.
HUF76419D3, HUF76419D3S
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVDSS IDSS IGSS VGS(TH) rDS(ON) ID = 250A, VGS = 0V (Figure 12) ID = 250A, VGS = 0V , TC = -40oC (Figure 12) Zero Gate Voltage Drain Current VDS = 55V, VGS = 0V VDS = 50V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A (Figure 11) ID = 20A, VGS = 10V (Figures 9, 10) ID = 20A, VGS = 5V (Figure 9) ID = 19A, VGS = 4.5V (Figure 9) THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA TO-251,TO-252 2.00 100
oC/W oC/W
TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
60 55 -
-
1 250 100 3 0.037 0.043 0.046
V V A A nA
VGS = 16V
1 -
0.031 0.036 0.038
V
SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 30V, ID = 20A, Ig(REF) = 1.0mA (Figures 14, 19, 20) VDD = 30V, ID = 20A VGS = 10V, RGS = 13 (Figures 16, 21, 22) VDD = 30V, ID = 19A VGS = 4.5V, RGS = 13 (Figures 15, 21, 22) 12 124 28 50 205 115 ns ns ns ns ns ns
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance 900 250 45 pF pF pF 23 12.5 0.9 2.7 5.9 27.5 15 1.05 nC nC nC nC nC 6.5 35 50 50 62 150 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD trr QRR ISD = 20A ISD = 10A Reverse Recovery Time Reverse Recovered Charge ISD = 20A, dISD/dt = 100A/s ISD = 20A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.0 74 200 UNITS V V ns nC
4-2
HUF76419D3, HUF76419D3S Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) 25
20 VGS = 10V 15 VGS = 4.5V 10
5
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
SINGLE PULSE 0.01 10-5 10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
100
VGS = 10V
I = I25
175 - TC 150
VGS = 5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
10
FIGURE 4. PEAK CURRENT CAPABILITY
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HUF76419D3, HUF76419D3S Typical Performance Curves
200 IAS, AVALANCHE CURRENT (A) 100 ID, DRAIN CURRENT (A)
(Continued)
200 100
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100s OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 200
10
10 STARTING TJ = 150oC
STARTING TJ = 25oC
1ms
10ms
1 0.01 0.1 1 10 100 tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
50 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
50 VGS = 10V ID, DRAIN CURRENT (A) 40 VGS = 5V 30 VGS = 3.5V 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 10 TC = 25oC 0 VGS = 3V 4 VGS = 4V
40 ID, DRAIN CURRENT (A)
30
20 TJ = 25oC 10 TJ = 175oC 0 1 2 3 4 5 TJ = -55oC
0 VGS, GATE TO SOURCE VOLTAGE (V)
1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
50 NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC ID = 10A 40 ID = 20A
2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0
45
1.5
35
1.0 VGS = 10V, ID = 20A 0.5 -80 -40 0 40 80 120 160 200
30
25 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
4-4
HUF76419D3, HUF76419D3S Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.0
(Continued)
1.2
ID = 250A
1.1
0.8
1.0
0.6
0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200
0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
10 VGS , GATE TO SOURCE VOLTAGE (V)
2000 CISS = CGS + CGD 1000 C, CAPACITANCE (pF)
VDD = 30V 8
6
COSS CDS + CGD 100
4
2
WAVEFORMS IN DESCENDING ORDER: ID = 20A ID = 10A
VGS = 0V, f = 1MHz 20 0.1
CRSS = CGD 60
0 0 5 10 15 20 Qg, GATE CHARGE (nC) 25 30
1.0 10 VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
300 VGS = 4.5V, VDD = 30V, ID = 19A 250 SWITCHING TIME (ns) 200 150 tf 100 td(OFF) 50 td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () SWITCHING TIME (ns) tr
180 VGS = 10V, VDD = 30V, ID = 20A 150 td(OFF) 120 90 tr 60 30 0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50 tf
td(ON)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
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HUF76419D3, HUF76419D3S Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10% 90%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH 50%
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
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HUF76419D3, HUF76419D3S PSPICE Electrical Model
.SUBCKT HUF76419D3 2 1 3 ;
CA 12 8 1.20e-9 CB 15 14 1.20e-9 CIN 6 8 8.49e-10
DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18
rev 8 July 1999
LDRAIN 10 RSLC1 51 ESLC 50 DRAIN 2
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 68.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 2.51e-9 LSOURCE 3 7 3.57e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
S1A LGATE GATE 1 RLGATE
RSLC2
5 51
ESG + EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S2A RBREAK 17 18 RVTEMP CB + 6 8 EDS 5 8 14 IT 19 7 SOURCE 3
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.12e-2 RGATE 9 20 3.12 RLDRAIN 2 5 10 RLGATE 1 9 25.1 RLSOURCE 3 7 35.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.60e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
12 S1B CA
13 8 13
14 13 S2B +
15
EGS
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*98),3))} .MODEL DBODYMOD D (IS = 8.51e-13 RS = 1.03e-2 TRS1 = 1.08e-3 TRS2 = 9.91e-7 CJO = 1.06e-9 TT = 4.90e-8 M = 0.5) .MODEL DBREAKMOD D (RS = 2.39e-1 TRS1 = 1.23e-4 TRS2 = 1.11e-6) .MODEL DPLCAPMOD D (CJO = 7.42e-10 IS = 1e-30 M = 0.85) .MODEL MMEDMOD NMOS (VTO = 1.98 KP = 2.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.12) .MODEL MSTROMOD NMOS (VTO = 2.33 KP = 50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.75 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 31.2 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.14e-3 TC2 = 1.02e-9) .MODEL RDRAINMOD RES (TC1 = 1.19e-2 TC2 = 3.22e-5) .MODEL RSLCMOD RES (TC1 = 9.91e-4 TC2 = 3.17e-5) .MODEL RSOURCEMOD RES (TC1 = 1.0e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.34e-3 TC2 = -5.33e-6) .MODEL RVTEMPMOD RES (TC1 = -1.45e-3 TC2 = 0) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.5 VOFF= -3.0) VON = -3.0 VOFF= -5.5) VON = -0.2 VOFF= 0.1) VON = 0.1 VOFF= -0.2)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
4-7
+
-
RDRAIN 21 16
DBODY
MWEAK MMED
VBAT +
8 22 RVTHRES
HUF76419D3, HUF76419D3S SABER Electrical Model
REV 8 July 1999 template huf76419d3 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 8.51e-13, cjo = 1.06e-9, tt = 4.90e-8, m = 0.50) d..model dbreakmod = () d..model dplcapmod = (cjo = 7.42e-10, is = 1e-30, m = 0.85 ) m..model mmedmod = (type=_n, vto = 1.98, kp = 2.10, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.33, kp = 50, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.75, kp = 0.08, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -3.0) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3.0, voff = -5.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.1) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.1, voff = -0.2) c.ca n12 n8 = 1.2e-9 c.cb n15 n14 = 1.2e-9 c.cin n6 n8 = 8.49e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 2.51e-9 l.lsource n3 n7 = 3.57e-9
GATE 1 RLGATE CIN LGATE
LDRAIN DPLCAP 10 RSLC1 51 RSLC2 ISCL RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED MSTRO 8 EBREAK + 17 18 71 RDBODY 5 DRAIN 2
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBODY
-
LSOURCE 7 RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
S1A S2A 14 13 S2B 13 + EGS 6 8 EDS CB + 5 8 14 15
SOURCE 3
RSOURCE 12 RBREAK 17 18 RVTEMP 19 IT
res.rbreak n17 n18 = 1, tc1 = 1.14e-3, tc2 = 1.02e-9 res.rdbody n71 n5 = 1.03e-2, tc1 = 1.08e-3, tc2 = 9.91e-7 res.rdbreak n72 n5 = 2.39e-1, tc1 = 1.23e-4, tc2 = 1.11e-6 res.rdrain n50 n16 = 1.12e-2, tc1 = 1.19e-2, tc2 = 3.22e-5 res.rgate n9 n20 = 3.12 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 25.1 res.rlsource n3 n7 = 35.7 res.rslc1 n5 n51 = 1e-6, tc1 = 9.91e-4, tc2 =3.17e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.60e-2, tc1 = 1e-3, tc2 =0 res.rvtemp n18 n19 = 1, tc1 = -1.45e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = -2.34e-3, tc2 = -5.33e-6 spe.ebreak n11 n7 n17 n18 = 68.35 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
13 8 S1B
CA
VBAT +
-
-
8 RVTHRES
22
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3)) } }
4-8
HUF76419D3, HUF76419D3S SPICE Thermal Model
REV 16 July 1999 HUF76419D3T CTHERM1 th 6 1.35e-3 CTHERM2 6 5 1.50e-2 CTHERM3 5 4 5.50e-3 CTHERM4 4 3 3.00e-3 CTHERM5 3 2 1.20e-2 CTHERM6 2 tl 3.00 RTHERM1 th 6 1.32e-2 RTHERM2 6 5 3.30e-2 RTHERM3 5 4 9.28e-2 RTHERM4 4 3 5.21e-1 RTHERM5 3 2 7.86e-1 RTHERM6 2 tl 1.04e-1
RTHERM1 CTHERM1
}
th
JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF76419D3T
4
template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.35e-3 ctherm.ctherm2 6 5 = 1.50e-2 ctherm.ctherm3 5 4 = 5.50e-3 ctherm.ctherm4 4 3 = 3.00e-3 ctherm.ctherm5 3 2 = 1.20e-2 ctherm.ctherm6 2 tl = 3.00 rtherm.rtherm1 th 6 = 1.32e-2 rtherm.rtherm2 6 5 = 3.30e-2 rtherm.rtherm3 5 4 = 9.28e-2 rtherm.rtherm4 4 3 = 5.21e-1 rtherm.rtherm5 3 2 = 7.86e-1 rtherm.rtherm6 2 tl = 1.04e-1
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com
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